The present invention relates generally to design automation, and relates more particularly to statistical simulation of memory and logic designs.
With deep technology scaling, statistical simulations play a key role in the analysis of state of the art memory and logic designs. Threshold voltage variation due to random dopant fluctuation, stress, bias temperature instability (BTI) variations, and telegraphic noise, along with other sources of process variation (e.g., mobility, oxide thickness, device length, width variations, and the like), can all affect the design yield. For instance, threshold voltage mismatch often causes stability, functionality, and performance degradation in memory designs under fail probabilities of less than one part per million.
Various techniques including Monte Carlo techniques or fast Monte Carlo methods are used to analyze the statistical behavior of designs. To speed up the statistical simulations, fast simulators and current source models can replace traditional simulation programs with integrated circuit emphasis (SPICE) simulators. Statistical simulations for yield analysis purposes (especially when dealing with rare fail events of memory designs), however, invoke many device instances (devices also span a large variability space) and require extreme accuracy; hence, the model pre-tabulation costs can be high, and reliance on early Berkeley short-channel insulated gate field effect transistor (IGFET) models (BSIMs) may prove inaccurate. This is especially true during the design optimization cycle, when multiple cell design choices may be under consideration.